/*-----------------------------------------
file name  : rdy_if.sv
created    : 2025/10/04 10:39:12
modified   : 2025-10-08 21:36:50
description: 
notes      : 
author     : yyrwkk
-----------------------------------------*/
interface rdy_if;
    logic rdy  ;
    logic clk  ; 
    logic rstn ;

`ifdef RDY_MON_CHECK
    logic vld  ;
    logic [`VLD_RDY_DATA_WIDTH-1:0] vld_rdy_data;
`endif

clocking mon @(posedge clk );
    default input #1ns output #1ns;
    input rdy ;

`ifdef RDY_MON_CHECK
    input vld ;
    input [`VLD_RDY_DATA_WIDTH-1:0] vld_rdy_data;
`endif

endclocking

clocking drv @(posedge clk );
    default input #1ns output #1ns;
    output rdy;
endclocking

`ifdef RDY_MON_CHECK
    `assert_handshake(clk,rstn,"vld_rdy",vld,vld_rdy_data,rdy)
`endif

endinterface
